EV Group just announced that they will be working with Applied Materials (AMAT) to develop thin wafer bonding technologies that will  be used to make through-silicon vias  in three-dimensional integrated circuit (3D IC) packaging applications.

Through-silicon vias technology involves stacking chips vertically to increase package density in electronic equipment. This allow for smaller devices that can do more with less power, but there are problems with the existing technology. The wafers that are used are too thin to hold up during the manufacturing process, so Applied Materials and EV Group will be looking at ways to use carrier wafers to support them during this period.

In a press release, executives from both companies commented on the effort:

“This is a continuation of our strategy to form alliances with leading equipment suppliers such as EVG to deliver fully-characterized TSV process flows to accelerate customers’ time to market,” said Hans Stork, group vice president and chief technology officer of Applied’s Silicon Systems Group. “We look forward to working with EVG at Applied’s Maydan Technology Center in advancing this disruptive technology and expediting the adoption of TSVs for mainstream manufacturing.”

“We are excited to collaborate with an industry leader like Applied, to expedite temporary bonding and debonding capabilities for 3D IC development,” said Markus Wimplinger, Corporate Technology Development and IP Director at EV Group “As a co-founder of EMC-3D, EVG is committed to the consortium’s mission to develop cost-effective and manufacturable TSVs for advanced semiconductors. This opportunity to work with Applied complements those efforts and brings us closer to realizing 3D IC production for our customers.”

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